1. Field of Invention
The present invention relates to layout of dies on a silicon wafer. Methods are described for optimal use of a stepper to produce dies taking into account the number of exposures required and usable cells produced. The cost of producing chips from a single wafer is reduced by optimal use of the stepper.
2. Related Art
A semiconductor device is fabricated by a lengthy sequence of complex physic-chemical processes on the surface of a single-crystal silicon wafer. The wafer fabrication operations (generally over 500 separate operations) basically include photolithography (the key patterning step), thin-film-etching, thin-film deposition, and oxidation. After a wafer is fabricated, the wafer is then sawed into dies, tested, and the good dies are sent to assembly to be mounted into packages. Extensive discussions of semiconductor manufacturing can be found, for example, in Wolf S., and Tauber, R. N., Silicon Processing for the VLSI Era: Volume 1 Process Technology, California: Sunset Beach, Lattice Press (1986). During the photolithography process, the area of the wafer that is exposed each time by the stepper is called a cell. One cell usually contains multiple dies.
Wafer fabs compete by lowering die costs, thereby taking advantage of significant capital investments and fixed operating costs. Many efforts have focused on improved exposure patterns to generate increased yields. That is, profit can be improved by exposing a wafer in a pattern that maximizes the number of gross dies per wafer and minmizig the wasted unused wafer area.
Automation of wafer exposure pattern layout, including driving a stepper pursuant to an optimized exposure pattern has received very little attention. A paper by A. V. Ferris-Prabhu, entitled xe2x80x9cAn Algebraic Expression to Count the Number of Chips on a Wafer,xe2x80x9d IEEE Circuits and Devices Magazine, pp. 37-39, January 1989, presents an algebraic expression that relates the die number of the wafer diameter and to the geometric parameters of the die. However, this paper does not present a method or apparatus for optimal wafer exposure patterning. Overall, little research has been conducted which identifies or attempts to solve the wafer exposure problem.
One aspect of the present invention is using a stepper or other wafer patterning device to create a pattern of cells on the surface of a wafer having a baseline, alignment marks, and an unusable border at the edge of the wafer. The alignment marks typically appear on the surface of the wafer. The baseline may be a construct, rather than a surface feature. This method includes defining a pattern on the wafer surface including alignment regions, center and corner regions in quadrants, and creating a pattern on the wafer surface using the defined regions. The alignment regions may extend outward from the reference marks parallel to a baseline. The baseline may pass through the alignment marks or may be parallel to a flat, if the wafer has a flat edge. The cells are preferably test located in the center and corner regions. A preferred cell pattern is selected after evaluation based on the number of exposures and quality of the cells created. One cell may include multiple dies. The quality of cells created may take into account the number of usable dies and location of the dies on the wafer, such as the distance between the dies and the edge of the wafer.
Another aspect of the present invention is a method of transmitting an exposure pattern from a processor to a stepper or other wafer patterning device in accordance with the method described above. According to this aspect of the invention, the pattern is determined in device separate from the stepper and then transmitted to the stepper.
A further aspect of the present invention is preparing an exposure pattern to be communicated from a processor to a stepper or other wafer patterning device. According to this aspect of the invention, the pattern is determined in a device separate from the stepper and recorded on memory. The memory may later be accessed by the stepper or an intermediate device for purposes a transmitting the pattern to the stepper.
The present invention may alternatively be embodied in device, such as a processor with an input for receiving locations of a baseline, first and second referent marks and a border along the edge of wafer, logic utilizing the processor to an define a pattern on surface of the wafer, including alignment regions and center and corner regions, and memory to receive a defined pattern. This device may further include a wafer patterning device in communication with the memory. Both the processor and memory may be incorporated directly into a wafer patterning device.